MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 185

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

BRK—Break Character Received
CCR—Control Character Received
BSY—Busy Condition
TX—Tx Buffer
RX—Rx Buffer
4.5.11.17 UART MASK Register
The SCC mask register (SCCM) is referred to as the UART mask register when the SCC is
operating as a UART. It is an 8-bit read-write register with the same bit formats as the UART
event register. If a bit in the UART mask register is a one, the corresponding interrupt in the
event register will be enabled. If the bit is zero, the corresponding interrupt in the event reg-
ister will be masked. This register is cleared upon reset.
4.5.11.18 S-Records Programming Example
In the following paragraphs, an example of a downloading application is given that utilizes
an SCC channel as a UART controller. The application performs downloads and uploads of
S records between a host computer and an intelligent peripheral through a serial asynchro-
nous line.
The S records are strings of ASCII characters that begin with `S' and end in an end-of-line
character. This characteristic will be used to impose a message structure on the communi-
cation between the devices. Note that each device may also transmit XON and XOFF char-
acters for flow control, which do not form part of the program being uploaded or downloaded.
The UART mode register should be set as required, with the freeze (FRZ) bit cleared and
the enable transmitter/receiver (ENT, ENR) bits set. Receive buffers should be linked to the
receive buffer table with the interrupt (I) bit set. For simplicity, assume that the line is not
multidrop (no addresses are transmitted) and that each S record will fit into a single data
buffer.
MOTOROLA
A break character was received.
A control character was received (with reject (R) character = 1) and stored in the receive
control character register (RCCR).
A character was received and discarded due to lack of buffers. The receiver automatically
enters hunt mode immediately if in the multidrop mode. The latest that an Rx BD can be
made empty (have its empty bit set) and still avoid the busy condition is the middle of the
stop bit of the first character to be stored in that buffer.
A buffer has been transmitted over the UART channel. If CR = 1 in the Tx BD, this bit is
set no sooner than when the last data bit of the last character in the buffer begins to be
transmitted. If CR = 0, this bit is set after the last character was written to the transmit
FIFO.
A buffer has been received over the UART channel. This event occurs no sooner than the
middle of the first stop bit of the character that causes the buffer to be closed.
MC68302 USER’S MANUAL
Communications Processor (CP)
4-65