MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 69

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Table 3-3 indicates the interrupt levels available in both normal and dedicated modes. This
table also shows the IPL2–IPL0 encoding that should be provided by external logic for each
EXRQ interrupt level in normal mode. For the dedicated mode, this table shows the IMP in-
put pins (IRQ7, IRQ6, and IRQ1) that should be asserted by an external device according
to the desired interrupt priority level.
3.2.2.2 INRQ Interrupt Source Priorities
Although all INRQ interrupts are presented at level 4, the interrupt controller further organiz-
es interrupt servicing of the 15 INRQ interrupts according to the priorities illustrated in Table
3-4. The interrupt from the port B pin 11 (PB11) has the highest priority, and the interrupt
from the port B pin 8 (PB8) has the lowest priority. A single interrupt priority within level 4 is
associated with each table entry. The IDMA entry is associated with the general-purpose
DMA channel only, and not with the SDMA channels that service the SCCs. Those interrupts
are reported through each individual SCC channel or, in the case of a bus error, through the
SDMA channels bus error entry.
3.2.2.3 Nested Interrupts
The following rules apply to nested interrupts:
MOTOROLA
1. The interrupt controller responds to all EXRQ and INRQ interrupts based upon their
assigned priority level. The highest priority interrupt request is presented to the
M68000 core for servicing. After the vector number corresponding to this interrupt is
passed to the core during an interrupt acknowledge cycle, an INRQ interrupt request
is cleared in IPR. (EXRQ requests must be cleared externally.) The remaining interrupt
*
7 (Highest)
6
5
4
3
2
1 (Lowest)
Priority level not available to an external device in this mode.
Table 3-4. INRQ Prioritization within Interrupt Level 4
Priority
Level
Priority
Highest
Lowest
Level
Table 3-3. EXRQ and INRQ Prioritization
General-Purpose Interrupt 3 (PB11)
General-Purpose Interrupt 2 (PB10)
SCC1
SDMA Channels Bus Error
IDMA Channel
SCC2
Timer 1
SCC3
General-Purpose Interrupt 1 (PB9)
Timer 2
SCP
Timer 3
SMC1
SMC2
General-Purpose Interrupt 0 (PB8)
Error
Normal Mode
IPL2–IPL0
MC68302 USER’S MANUAL
Interrupt Source Description
100
101
110
000
001
010
*
IRQ7, IRQ6, IRQ1
Dedicated Mode
IRQ7
IRQ6
IRQ1
*
*
*
*
System Integration Block (SIB)
Interrupt
Multiple
Events
Interrupt
Source
Yes
Yes
Yes
Yes
Yes
Yes
EXRQ
EXRQ
EXRQ
EXRQ
EXRQ
EXRQ
No
No
No
No
No
No
No
No
No
INRQ
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