MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 259

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Monitor Channel Protocol
SMC1 Reception
SMC2 Controls the GCI Command/Indication (C/I) Channel
4.7.2 SMC Programming Model
The operating mode of both SMC ports is defined by SMC mode, which consists of the lower
eight bits of SPMODE. As previously mentioned, the upper eight bits program the SCP.
MOTOROLA
The SMC1 receiver can be programmed to work in one of two modes:
Transparent Mode
Monitor Channel Protocol
SMC2 Transmission
SMC2 Reception
In this mode, SMC1 transmits the data and handles the A and E control bits according
to the GCI monitor channel protocol. When using the monitor channel protocol, the
user may issue the TIMEOUT command to solve deadlocks in case of bit errors in
the A and E bit positions on data line. The IMP will transmit an abort on the E bit.
In this mode, SMC1 receives the data, moves the A and E control bits transparently
into the SMC1 receive BD, and generates a maskable interrupt. The SMC1 receiver
discards new data when the M68000 core has not read the receive BD.
In this mode, SMC1 receives data and handles the A and E control bits according to
the GCI monitor channel protocol. When a received data byte is stored by the CP in
the SMC1 receive BD, a maskable interrupt is generated.
When using the monitor channel protocol, the user may issue the TRANSMIT
ABORT REQUEST command. The IMP will then transmit an abort request on the A
bit.
The M68000 core writes the data byte into the SMC2 Tx BD. SMC2 will transmit the
data continuously on the C/I channel to the physical layer device.
The SMC2 receiver continuously monitors the C/I channel. When a change in data is
recognized and this value is received in two successive frames, it will be interpreted
as valid data. The received data byte is stored by the CP in the SMC2 receive BD,
and a maskable interrupt is generated.
The receive and transmit clocks are derived from the same physical clock (L1CLK)
and are only active while serial data is transferred between the SMC controllers and
the serial interface.
When SMC loopback mode is chosen, SMC transmitted data is routed to the SMC
receiver. Transmitted data appears on the L1TXD pin, unless the SDIAG1–SDIAG0
bits in the SIMODE register are programmed to “loopback control” (see 4.4 Serial
Channels Physical Interface).
—
7
SMD3 SMD2 SMD1 SMD0 LOOP
6
MC68302 USER’S MANUAL
5
4
3
2
EN2
1
Communications Processor (CP)
EN1
0
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