MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 177
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
FRZ—Freeze Transmission
CL—Character Length
RTSM—RTS Mode
SL—Stop Length
COMMON SCC MODE BITS—see 4.5.3 SCC Mode Register (SCM) for a description of the
DIAG1, DIAG0, ENR, ENT, MODE1, and MODE0 bits.
4.5.11.14 UART Receive Buffer Descriptor (Rx BD)
The CP reports information about each buffer of received data by its BDs. The Rx BD is
shown in Figure 4-20. The CP closes the current buffer, generates a maskable interrupt, and
starts to receive data in the next buffer due to any of the following events:
MOTOROLA
This bit allows the user to halt the UART transmitter and to continue transmission from the
next character in the buffer at a later time.
This bit selects the number of the stop bits transmitted by the UART. The receiver is al-
ways enabled for one stop bit. Fractional stop bits are configured in the DSR (see
4.5.11.12 Fractional Stop Bits).
1. Reception of a user-defined control character (when reject (R) bit = 0)
2. Detection of an error during message processing
3. Detection of a full receive buffer
4. Reception of a programmable number of consecutive IDLE characters
10 = The DDCMP protocol is implemented over the asynchronous channel.
11 = Multidrop mode is enabled as in the 01 case, and the IMP automatically checks
0 = Normal operation (or resume transmission after FRZ is set).
1 = The UART completes transmission of any data already transferred to the UART
0 = 7-bit character length. On receive, bit 7 in memory is written as zero. On transmit,
1 = 8-bit character length
0 = RTS is asserted whenever the transmitter is enabled and there are characters to
1 = RTS is asserted whenever the transmitter is enabled (the ENT bit is set).
0 = One stop bit
1 = Two stop bits
FIFO (up to three characters) and then stops transmitting data. The UART contin-
ues to receive normally.
bit 7 in memory is a don't care.
transmit. RTS is negated after the last stop bit of a transmitted character when both
the shift register and the transmit FIFO are empty. RTS is also negated at the end
of a buffer to guarantee accurate reporting of the CTS bit in the BD.
ceives the address character and writes it to a new buffer. No address recognition
is performed.
the address of the incoming address character and either accepts or discards the
data following the address.
MC68302 USER’S MANUAL
Communications Processor (CP)
4-57
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