MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 209

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

B—BCS Expected
H—Enter Hunt Mode
4.5.13.6 BSYNC-BISYNC SYNC Register
The 16-bit, memory-mapped, read-write BSYNC register is used to define the BISYNC strip-
ping and insertion of the SYNC character. When an underrun occurs during message trans-
mission, the BISYNC controller will insert SYNC characters until the next data buffer is
available for transmission. When the BISYNC receiver is not in hunt mode and a SYN1 char-
acter has been received and discarded, the receiver will discard a SYNC character if the val-
id (V) bit is set.
4.5.13.7 BDLE-BISYNC DLE Register
The 16-bit, memory-mapped, read-write BDLE register is used to define the BISYNC strip-
ping and insertion of the DLE character. When the BISYNC controller is in transparent mode
and an underrun occurs during message transmission, the BISYNC controller inserts DLE-
SYNC pairs until the next data buffer is available for transmission.
When the BISYNC receiver is in transparent mode and a DLE character is received, the re-
ceiver discards this character and excludes it from the BCS if the valid (V) bit is set. If the
second (next) character is a SYNC character, the BISYNC controller discards it and ex-
MOTOROLA
15
V
0 = The character is written into the receive buffer. The buffer is then closed.
1 = The character is written into the receive buffer. The receiver waits for one LRC or
0 = The BISYNC controller will maintain character synchronization after closing this
1 = The BISYNC controller will enter hunt mode after closing the buffer. When the B bit
14
0
two CRC bytes of BCS and then closes the buffer. This should be used for ETB,
ETX, and ITB.
buffer.
is set, the controller will enter hunt mode after the reception of the BCS.
In tables with eight control characters, E should be zero in all
eight positions.
A maskable interrupt is generated after the buffer is closed.
Normal Bisync operation requires that SYN1=SYN2=SYNC
(and the V bit must be set in the BISYNC SYNC register).
When using 7-bit characters with parity, the parity bit should be
included in the SYNC register value.
13
0
12
0
11
0
10
0
MC68302 USER’S MANUAL
9
0
NOTE
NOTE
NOTE
8
0
7
6
5
Communications Processor (CP)
4
SYNC
3
2
1
4-89
0