MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 116

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
FRZ1—Freeze Timer 1 Enable
FRZ2—Freeze Timer 2 Enable
FRZW—Freeze Watchdog Timer Enable
No other MC68302 peripherals are directly affected by the freeze logic; however, conse-
quential errors such as receiver overruns in the SCC FIFOs may occur due to the CP main
controller being disabled. Note that use of the freeze logic does not clear any IPR bits that
were already set.
3.10 DYNAMIC RAM REFRESH CONTROLLER
The communications processor (CP) main (RISC) controller may be configured to handle
the dynamic RAM (DRAM) refresh task without any intervention from the M68000 core. Use
of this feature requires a timer or SCC baud rate generator (either from the MC68302 or ex-
ternally), the I/O pin PB8, and two transmit buffer descriptors from SCC2 (Tx BD6 and Tx
BD7).
The DRAM refresh controller routine executes in 25 clock cycles. Assuming a refresh cycle
every 15.625 s, two wait state DRAMs, and a 16.67-MHz EXTAL frequency, this routine
uses about 10 percent of the microcontroller bandwidth and 4 percent of the M68000 bus
bandwidth. The refresh cycle will not be executed during a period that a bus exception (i.e.,
RESET, HALT, or BERR) is active. The refresh cycle is a standard M68000-type read cycle
(an SDMA byte read cycle). It does not generate row address strobe (RAS) and column ad-
dress strobe (CAS) to the external DRAM. These functions require an external PAL. Use of
the DRAM refresh controller will slightly reduce the maximum possible serial data rates of
the SCCs.
3.10.1 Hardware Setup
An output of timer 1 or timer 2 (the TOUT pin) or one of the SCC's baud rate generator out-
puts (BRG3–BRG1) should be connected externally to PB8. A high-to-low transition on this
edge causes a request to be generated to the main controller to perform one refresh cycle.
The DRAM refresh request takes priority over all SCC channels and commands given to the
CP command register.
A block diagram of an MC68302 DRAM system is shown in Figure 3-13. The MC68302 gen-
erates standard M68000 read and write cycles that must be converted to DRAM read and
write cycles. The address buffers provide the multiplexing of the row and column addresses
3-66
After system reset, this bit defaults to zero.
After system reset, this bit defaults to zero.
After system reset, this bit defaults to zero.
0 = Freeze timer 1 logic is disabled.
1 = Freeze timer 1 logic is enabled.
0 = Freeze timer 2 logic is disabled.
1 = Freeze timer 2 logic is enabled.
0 = Freeze watchdog timer logic is disabled.
1 = Freeze watchdog timer logic is enabled.
MC68302 USER’S MANUAL
MOTOROLA