MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 75
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
ET7—IRQ7 Edge-/Level-Triggered
ET6—IRQ6 Edge-/Level-Triggered
ET1—IRQ1 Edge-/Level-Triggered
MOTOROLA
This bit is valid only in the dedicated mode.
This bit is valid only in the dedicated mode.
This bit is valid only in the dedicated mode.
0 = Level-triggered. An interrupt is made pending when IRQ7 is low.
1 = Edge-triggered. An interrupt is made pending when IRQ7 changes from one to
0 = Level-triggered. An interrupt is made pending when IRQ6 is low.
1 = Edge-triggered. An interrupt is made pending when IRQ6 changes from one to
0 = Level-triggered. An interrupt is made pending when IRQ1 is low.
zero (falling edge).
zero (falling edge).
The M68000 always treats level 7 as an edge-sensitive interrupt.
Normally, users should not select the level-triggered option. The
level-triggered option is useful when it is desired to make the ne-
gation of IRQ7 cause the IOUT2–IOUT0 pins to cease driving a
level 7 interrupt request when the MC68302 is used in the dis-
able CPU mode. This situation is as follows:
For a slave-mode MC68302, when it is triggered by IRQ1, IRQ6,
or IRQ7 to generate an interrupt, its interrupt controller will out-
put the interrupt request on pins IOUT2–IOUT0 to another pro-
cessor (MC68302, MC68020, etc.) For cases when the slave
MC68302 does not generate a level 4 vector (i.e., the VGE bit is
cleared), one must set the ET1, ET6, and ET7 bits to level-trig-
gered and then negate the IRQ1, IRQ6, and IRQ7 lines external-
ly in the interrupt handler code. If the ET1, ET6, and ET7 bits are
set to edge-triggered and the VGE bit is clear, the IOUT2–IOUT0
pins will never be cleared.
While in disable CPU mode during the host processor interrupt
acknowledge cycle for IRQ6, if IRQ6 is not continuously assert-
ed, the interrupt controller will still provide the vector number
(and DTACK) according to the IV6 bit. The IACK6 falling edge
may be used externally to negate IRQ6.
MC68302 USER’S MANUAL
NOTE
NOTE
System Integration Block (SIB)
3-25
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