MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 263

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

E—Empty
Bits 14–6—These bits are reserved and should be set to zero by the M68000 core.
C/I—Command/Indication Channel Data
Bits 1–0—The CP always writes these bits with zeros.
4.7.4.4 SMC2 Transmit Buffer Descriptor
In the IDL mode, this BD is identical to the SMC1 transmit BD. In the GCI mode, SMC2 is
used to control the C/I channel.
R—Ready
Bits 14–6—Reserved for future use; should be set to zero by the user.
C/I—Command/Indication Channel Data
Bits 1–0—These bits should be written with zeros by the M68000 core.
4.7.5 SMC Interrupt Requests
SMC1 and SMC2 send individual interrupt requests to the IMP interrupt controller when one
of the respective SMC receive buffers is full or when one of the SMC transmit buffers is emp-
ty. Each of the two interrupt requests from each SMC is enabled when its respective SMC
channel is enabled in the SPMODE register. Interrupt requests from SMC1 and SMC2 can
be masked in the interrupt mask register. See 3.2 Interrupt Controller for more details.
MOTOROLA
15
R
0 = This bit is cleared by the CP to indicate that the data bits associated with this BD
1 = This bit is set by the M68000 core to indicate that the data bits associated with this
0 = This bit is cleared by the CP after transmission to indicate that the BD is now avail-
1 = This bit is set by the M68000 core to indicate that the data associated with this BD
14
are now available to the M68000 core.
BD have been read.
able to the M68000 core.
is ready for transmission.
Additional data received will be discarded until the empty bit is
set by the M68000 core.
RESERVED
MC68302 USER’S MANUAL
NOTE
6
5
Communications Processor (CP)
C/I
2
1
0
4-143
0
0