L64704 LSI Logic Corporation, L64704 Datasheet - Page 10

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Tables
x
May 1997
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
A.1
A.2
A.3
A.4
A.5
B.1
B.2
C.1
C.2
C.3
C.4
3.1
3.2
3.3
3.4
4.1
4.2
5.1
5.2
5.3
Contents
Rev. letter
Code Word Structure
Forward Error Correction Data Path
122-bit Burst Example
(255, 255-2T) Code Performance
Descrambler Block Diagram
15-bit Shift Register
Inverting Sync Words in Descrambler
AC Test Load and Waveform for Standard Outputs
AC Test Load and Waveform for 3-State Outputs
L64704 Synchronous AC Timing
L64704 RESET Timing Diagram
L64704 Bus 3-State Delay Timing
L64704 Decoder Read Cycle
L64704 Decoder Write Cycle
L64704 100-Pin PQFP Pinout
100-Pin PQFP Mechanical Drawing (Sheet 1 of 2)
Quick Overview of the Serial Bus
Quick Overview of Serial Bus Write/Read Cycles
General Call Structure
Burst Write to Slave (Master-Transmitter, Slave-Receiver)
Single Read From Slave
Flow Diagram of Microcontroller Monitoring External Loops B-3
AGC Loop Control
Simplest Oscillator
Pierce Crystal Oscillator Circuit
A Third Overtone (Higher Frequency) Oscillator Circuit
A Low Frequency Range (kHz) Oscillator Circuit
Register Overview
Register Map
Group 3 Register Map
Group 4 Register Map
CLK/SCLK Ratio
Values for PLL_S, PLL_N, PLL_T, and PLL_M
M as a Function of CLK_DR and CLK_RATIO
Natural Frequency as a Function of M
Example of Data Rates
Copyright © 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
7-15
7-15
7-17
7-19
7-20
7-20
7-21
8-11
8-12
3-20
3-27
5-10
C-1
C-2
C-4
C-5
A-2
A-3
A-4
A-5
A-7
B-5
8-5
8-6
8-6
8-7
8-7
8-7
8-8
3-2
3-2
4-7
4-8
5-7
5-8