L64704 LSI Logic Corporation, L64704 Datasheet - Page 164

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 7.18
Descrambler Block
Diagram
Figure 7.19
15-bit Shift
Register
7-20
Scrambled
The following generator polynomial produces the pseudorandom bit
sequence in the Descrambler:
For initialization. a specific value is chosen for the 15-tap shift register
shown in
:
The encoder inverts every eighth MPEG transport sync word (0x47) to
generate a sync word (0xB8) that the decoder then uses to align the
Descrambler with the incoming data stream. The first bit of the PRBS is
applied to the first data bit following the inverting MPEG sync byte.
During the following seven noninverting MPEG sync words, the L64704
operates the Descrambler sequence generator, but does not modify the
data stream. The L64704 resets the Descrambler after every inverting
MPEG sync word.
The FEC Decoder Pipeline
Bit Stream
1
1 0 0 1 0 1 0 1 0 0 0 0 0 0 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+
x
14
Shift Register Initialization Sequence
Strobes
Frame
Control
+
x
Figure
15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
7.19.
Control Module
Shift Register
XOR
XOR
Strobes to
Pipeline
Control
Descrambled
Bit Stream