L64704 LSI Logic Corporation, L64704 Datasheet - Page 48

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L64704

Manufacturer Part Number
L64704
Description
Satellite Decoder Technical Manual 5/97
Manufacturer
LSI Logic Corporation
Datasheet

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3.4.2
System Status
Register (STS)
3-16
APR
1
FS_UL
D15
FS_LL
Reserved
The STS Register is a read-only register that provides the external micro-
controller access to status information about the L64704. It provides
information about what event caused the generation of an internal inter-
rupt condition. The interrupt status bits are set regardless of the enable
interrupt bits in the SMR Register. The internal status is updated every
L64704 OCLK. When the microcontroller reads the status, the current
information is buffered in a special purpose 16-bit STS buffer that locks
the STS value until the end of the microcontroller read operation.
Two consecutive read operations must be done to the same address to
get both bytes of the STS. The eight MSBs are the interrupts related to
the Demodulation function of the L64704, and the eight LSBs are the
interrupts related to the Forward Error Correction function of the L64704.
The status bits are reset after a hardware reset. They are also reset each
time that the register byte is read; when you read the eight LSBs, the
eight LSB interrupts are cleared, and when you read the eight MSBs, the
eight MSB interrupts are cleared. The register diagram below shows a
detailed description of the STS[15:8] register bits:
FS_UL
FS_LL
L64704 Registers
D14
CF_LLK
D13
Reserved Bit
This bit is reserved for LSI Logic internal use only. You
should always set this bit to 0.
Frequency Sweep Upper Limit Reached
The L64704 sets this bit when the upper limit of the
Frequency Sweep is reached.
Frequency Sweep Lower Limit Reached
The L64704 sets this bit when the lower limit of the
Frequency Sweep is reached.
FS_UL
0
1
FS_LL
0
1
CF_LK
D12
Definition
Frequency Sweep Status Unchanged
Frequency Sweep Upper Limit Reached
Definition
Frequency Sweep Status Unchanged
Frequency Sweep Lower Limit Reached
CP_LLK
D11
CP_LK
D10
AFC_LLK
D9
AFC_LK
D8
0
0
1

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