L64704 LSI Logic Corporation, L64704 Datasheet - Page 31

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

2.7
Control Signals
These signals control the operation of the L64704. They are not associ-
ated with any particular interface.
IDDTN
RESET
XCTR_IN
XCTR_OUT[3:0]
Control Signals
Test Pin
IDDTN is an LSI Logic internal test pin. Connect this pin
LOW for normal operation.
Reset
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the configuration registers. It performs the
same operation as the reset bits specified in
3.6.31, “Group 4, APR 36 External Output Control Bits
and Reset Register.”
Control Input Pin
The XCTR_IN pin is an external input control pin. It is
sensed by reading the corresponding bit in the Group 3,
APR 6 register.
Control Output Pins
The XCTR_OUT[3:0] pins are external output control
pins. They are set by programming the corresponding bits
in the Group 4, APR 36 register.
Section
Output
Input
Input
Input
2-9