L64704 LSI Logic Corporation, L64704 Datasheet - Page 121

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

5.6.2
Carrier Phase
Tracking
Figure 5.7
SNR Threshold vs.
ES/No
5.6.2.1 Phase Error Estimator
In QPSK mode (CON_SEL = 0; Group 4, APR 35), the phase error
detector implements two error estimators:
The microcontroller selects the estimator via the CAR_PED_SEL bit
(Group 4, APR 33). CAR_PED_SEL = 0 sets the DDML estimator;
CAR_PED_SEL = 1 sets the NDAML estimator.
In BPSK mode (CON_SEL = 1), the phase error detector implements a
single DDML estimator.
The phase detector uses two gain values depending on the signal to
noise ratio. The SNR is internally estimated and compared to an 8-bit
threshold; SNR_THS (Group 4, APR 22). The plot in
the relation between the SNR_THS parameter and the actual Es/No
(symbol energy to noise power density) seen in the circuit. The value
SNR_THS = 100 corresponding to an actual Es/No = 11 dB is recom-
mended. The result of the comparison of the estimated SNR to the
threshold is stored in the Demod_SNR bit (Group 3, APR 6, bit 7).
Carrier Synchronizer
a Non-data Aided Maximum Likelihood (NDAML) estimator
a Decision Directed Maximum Likelihood (DDML) estimator
250
200
150
100
50
0
0
* *
*
*
10
*
Es/No [dB]
SNR_THS
*
20
*
PWR_REF = 54
*
Figure 5.7
30
*
shows
5-17