L64704 LSI Logic Corporation, L64704 Datasheet - Page 107

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

5.2
DC Offset
Compensation
and Coupling to
ADC Output
Figure 5.2
Input Quantization
with AC Coupling
5.3
Decimation
Filters
The L64704 provides for an internal suppression of DC offsets on the I
and Q channels. To enable this function, set the PWR_BW bits (Group 4,
APR 20). This feature is particularly useful when using an integrated
front end that does not provide DC offset compensation pins and that
introduces small offsets.
The external analog to digital convertor must produce six-bit samples
that reflect the 32-positive values and 32-negative values as shown in
Figure
The L64704 implements two switchable decimation filters on each I and
Q branch: a 1/2-band filter and a 2/3-band filter. These two filters enable
the Analog to Digital Convertor (ADC) to operate at an oversampling ratio
of N = 2, 3, or 4. The filters generate 2/T-sampled I and Q streams from
the 3/T or 4/T sampled I and Q inputs. The resulting 2/T streams are
inputs for the matched filter.
To configure the decimation filters, the microcontroller should write one
of the following values to the CLK_DR[1:0] bits of the Clock Loop
Control 1 register (Group 4, APR14):
DC Offset Compensation and Coupling to ADC Output
CLK_DR = 0 for no decimation, N = 2
CLK_DR = 1 for decimation by 1/2, N = 4
CLK_DR = 2 for decimation by 2/3, N = 3
5.2. The six-bit samples are fed to the RI[5:0] and RQ[5:0] inputs.
3
1
5
-5
-1
-3
RI[5:0], RQ[5:0]
ADC
Input
5-3