L64704 LSI Logic Corporation, L64704 Datasheet - Page 38

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 3.1
Register-File
Structure
3-6
Figure 3.1
Group
To reduce the number of memory locations occupied by the L64704 in
microcontroller memory, the L64704 uses an Address Pointer Register
(APR). The APR has an auto-increment feature that simplifies the initial-
ization procedure and reduces the number of memory cycles needed to
read or write the registers. The address pointer and auto-increment
feature are used whenever you access Groups 2, 3, and 4. The L64704
automatically points to the next register entry after you complete an
access to one of these groups. When configuring or reading the config-
uration of groups 3 and 4, you will find it easier to initially set APR0 and
APR1 to zero and let the auto-increment mechanism step through all the
locations within the group.
For example: to access the PLL_N configuration register 0 (Group 4,
APR 0), first set APR0 = APR1 = 0
1, then set A[2:0] to 100
groups.
Internally, the L64704 has an 8-bit architecture. Most registers are eight
bits wide, while some are either 16- or 24-bits wide. All registers are
memory-mapped to the system with 8-bit resolution. When you are
accessing a register that is wider than 8 bits, you must read or write two
or three 8-bit sections: the least-significant byte (LSB) the middle-
significant byte (MB) and the most-significant byte (MSB). Each 8-bit sec-
tion is assigned a specific address, and therefore requires an individual
memory cycle during programming.
L64704 Registers
0
1
2
3
4
5
6
7
STATUS CNT
RESERVED
RESERVED
CONF REGS
RESERVED
SMR/STS
APR0
APR1
shows a simplified diagram of the L64704’s register file.
2
. Address A[2:0] selects Group 4 of the six APR
2
by writing a zero to addresses 0 and
0
1
2
...
10
11
0
1
2
4
5
6
7
8
...
31
32
33
34
35
36
Group 3:
Status Counters
Group 4:
Configuration Register