L64704 LSI Logic Corporation, L64704 Datasheet - Page 36

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Table 3.2 (Cont.)
Register Map
3-4
Group APR
4
(Sheet 3 of 4)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Bit(s)
7
5:4
3:2
1:0
7:5
3
2:0
7:0
7
4
3
2
1:0
6
4
3:0
7:0
7:0
2:0
7:0
2
1:0
7:0
7:0
7:0
3:0
7:0
7:0
L64704 Registers
R/W Description
R/W BCLKOUT Format
R/W Synchronization Status Select
R/W Synchronization States, Acquisition Mode SSA[1:0]
R/W Synchronization States, Tracking Mode
R/W Symbol Size for Viterbi Bypass Mode
R/W Descrambler Output Format
R/W Output Selector, OS[2:0]
W
R/W SYNC/SCLK Selector Bit
R/W Functional Outputs 3-stated
R/W CLK_LCF_Suppress in Timing Error
R/W Clock Outputs Polarity Swap
R/W Decimation Filter Select
R/W PCLK Bypass
R/W Power-Down
R/W Reference Period for Clock AFC
R/W CLK Input Nominal Frequency, Upper
R/W CLK Input Nominal Frequency, Lower
R/W Input Decimation Factor for RI & RQ
R/W Reference Power Level
R/W Internal DC Offset Compensation on I and
R/W Power Estimation Bandwidth
R/W Scale Factor for DEMI and DEMQ Outputs SCALE[7:0]
R/W SNR Estimator Threshold
R/W Carrier Loop DC Offset Comp. Value
R/W Reference Period for Carrier Frequency
R/W Gain of Carrier Loop Filter (P Term)
R/W Gain of Carrier Loop Filter (D Term)
Reset for PLL Module
Detector
Inputs
Q Signals
(CAR_DCLKP/N) Measurement
Acronym
BF
SSS[1:0]
SST[1:0]
BPS[2:0]
OF
OS[2:0]
PLL_RESET
SYNC/SCLK
F_OUT_HiZ
CLK_LCF_
Suppress
CLK_VCO_SWAP
CLK_DR[1:0]
PCLK_BP
PD
CLK_RP[3:0]
CLK_NF[15:8]
CLK_NF[7:0]
CLK_RATIO[2:0]
PWR_REF[7:0]
INT_DC
PWR_BW[1:0]
SNR_THS[7:0]
CAR_OFFSET[7:0]
CAR_RP[3:0]
CAR_KP[7:0]
CAR_KD[7:0]
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