L64704 LSI Logic Corporation, L64704 Datasheet - Page 88

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figure 4.4
Code Rate = 3/4
System; Different
OCLK and CLK
4.2
Channel Data
Input Interface
Figure 4.5
CLK Reference to
Channel Data Input
4-4
Figure 4.4
data processing rate in the decoding pipeline. Because the depuncturing
logic inserts extra symbols (erasures), the L64704 transmits the symbols
from the FIFO in small bursts at the higher clock rate (OCLK). After leav-
ing the Viterbi Decoder, the data stream becomes continuous at the
OCLK rate.
FIFO Output
Figure 4.4
tained, the incoming data stream is continuous, and the decoder fixes the
frequency of OCLK at twice that of CLK. Because the decoder reads the
FIFO at the OCLK frequency— which is greater than the Viterbi code
rate—the FIFO empties periodically. The data pipeline is designed to
handle such internal interruptions in the data stream without corrupting
data that is already being processed. As a consequence, the channel
output data appears in bursts at the OCLK rate, but on average maintains
the data rate imposed by the Viterbi Decoder. The DVALIDOUT signal
indicates when valid data is on the CO[7:0] output.
Figure 4.5
are referenced to CLK.
RI[5:0], RQ[5:0]
Channel Interfaces and Data Control
Viterbi Data
FIFO Input
Output
OCLK
CLK
CLK
shows how the channel data input signals RI[5:0] and RQ[5:0]
illustrates a case where the input data rate is set to 3/4 of the
shows a case in which the data rate ratios shown are main-
1
Hold
Setup
2
Sym 1
Sy 1
3
Sym 2
Dn
Sy2
Dn+1
4
Sym 3
Dn+2
Sy3
5
Sym 4
Dn+3
Sy4