L64704 LSI Logic Corporation, L64704 Datasheet - Page 197

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

B.3.1
Programming
the L64704
QPSK
Demodulator
Registers
This subsection describes how to program each of the L64704’s regis-
ters. The microcontroller addresses these registers as described in
tion 3.1, “L64704 Register Overview.”
Group 4, APR 14 – Set the lower four bits in the Clock Loop Control 1
register as shown in the following table.
Set Group 4, APR 14 to 0x00.
Group 4, APR 15 – The recommended value for CLK_RP[3:0] is 10.
Set Group 4, APR 15 to 0x0A.
Group 4, APR 16-17 – The recommended value for CLK_NF[15:0] is
43622, as computed from
Set APR 16 to 0xAA and APR 17 to 0x66.
Group 4, APR 18 – The recommended value for CLK_RATIO[2:0] is 0
for only 2 samples/symbol.
Set Group 4, APR 18 to 0x00.
Group 4, APR 19 – PWR_REF[7:0] = 84 is the recommended value if
L = 1. As discussed in
ence,”
p-to-p on the I and Q channels. The ratio S:R must be 1:1.7 when
PWR_REF = 84.
QPSK Demodulator Configuration Example
CLK_NF
Bits Setting Acronym
S
--- -
R
1:0
2
3
=
------- -
1.7
1
2 R is the ADC range p-to-p and 2 S is the input signal range
0
0
0
=
42.6 10 1024
------------------------------------------- -
CLK_DR[1:0]
CLK_VCO_SWAP
CLK_LCF_Suppress
10
Section 5.7.1, “ADC Range and Power Refer-
Equation 5.1
=
43622
Meaning
No decimation, oversampling ratio = 2.
CLK outputs not swapped.
AFC enabled.
on
page
5-6:
Sec-
B-9