L64704 LSI Logic Corporation, L64704 Datasheet - Page 8

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Figures
viii
May 1997
1.1
1.2
1.3
1.4
2.1
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Contents
Rev. letter
L64704 Block Diagram
Set-Top Decoder Box Block Diagram
Typical Receiver Block Diagram with L64704
Concatenated Decoding Performance for L64704
L64704 Logic Diagram
Register-File Structure
Issue a Hard Reset
Initialize APR0 and APR1 to Zero
Write Locations 0 and 1 in Group 4
Read Back Group 4
L64704 Clocking: Internal PLL
L64704 Clocking: External PLL
Code Rate = 1/2 System
Code Rate = 3/4 System; Different OCLK and CLK
CLK Reference to Channel Data Input
OCLK Reference to Channel Data Output
FSTARTOUT Related to Symbols
PLL Clock Generation
PLL Clock Synthesis
L64704 Functional Blocks in the Decoding Pipeline
Descrambler Serial Output Waveforms
Descrambler Parallel Output Format
Synchronization Stage 3 Output Waveforms
Reed-Solomon Decoder Output Waveforms
Deinterleaver Output Waveforms
Synchronization Stage 2 Output Waveforms
Viterbi Decoder Output Waveforms
Viterbi Depuncture/Synchronization Output Waveforms
QPSK Demodulator Output Waveforms
Demodulator Module and its Associated Circuitry
Input Quantization with AC Coupling
Clock Recovery Loop
Spectrum of Oversampled Signal
Carrier Recovery Loop
Frequency Sweeping
SNR Threshold vs. ES/No
Carrier Loop Filter Schematic
Copyright © 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
4-13
4-14
4-14
4-15
4-16
4-16
4-17
4-18
4-18
4-19
5-11
5-13
5-17
5-18
1-2
1-3
1-4
1-6
2-2
3-6
3-7
3-7
3-8
3-8
4-2
4-3
4-3
4-4
4-4
4-5
4-5
4-6
4-7
5-2
5-3
5-4
5-9