L64704 LSI Logic Corporation, L64704 Datasheet - Page 171

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Table 8.5 (Cont.)
L64704 Pin Description
Summary
8.2
AC Timing
Figure 8.1
AC Test Load and
Waveform for
Standard Outputs
Mnemonic
PWRP
READ
RESET
RI[5:0]
RQ[5:0]
SDATA
SYNC/SCLK
XCTR_OUT[3:0]
XCTR_IN
XOIN
XOOUT
(Sheet 2 of 2)
Description
Power Loop Control
Read Write
Chip Reset
Received I Samples
Received Q Samples
Serial Interface Data
Sync Status Flag
External Controls
External Controls
Input from External Crystal
Output to External Crystal
This section presents AC timing information for the L64704. During AC
testing, HIGH inputs are driven to 3.0 V and LOW inputs are driven at
0 V. For transitions between HIGH, LOW, and invalid states, timing mea-
surements are made at 1.5 V, as shown in
Output
For 3-state outputs, timing measurements are made from the point at
which the output turns ON or OFF. An output is ON when its voltage is
greater than 2.5 V or less than 0.5 V. An output is OFF when its voltage
is less than V
Figures
The numbers shown in the diagrams refer to parameters shown in
Table
AC Timing
8.6.
8.3
through
DD
Point
Test
– 0.5 V or greater than 0.5 V, as shown in
C
8.7
L
= 15 pF
show the various timing diagrams for the L64704.
Type
3-State Output
TTL Input with Pull-up
TTL Input
TTL Inputs
TTL Inputs
Bidirect
Output
CMOS Outputs
CMOS Input
CMOS Input
CMOS Output
1.5 V
Figure
8.1.
Drive (mA) Active
40
6
–
–
–
–
4
4
4
–
–
Figure
HIGH
HIGH
HIGH
MD94.361
8.2.
–
–
–
–
–
–
–
–
8-5