L64704 LSI Logic Corporation, L64704 Datasheet - Page 192

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

B.2
L64704 QPSK
Demodulator
Debugging Tips
B.2.1
AGC Loop
Table B.2
PWR_LVL Register
Setting
B-4
This section presents a debugging procedure to follow in case the
L64704’s QPSK demodulator fails to lock.
The AGC loop must lock first. When the AGC loop is closed, the signal
level at the Analog to Digital Convertor’s (ADC) input is 0.588 (1/1.7)
times the ADC range, assuming the PWR_REF register (Group 4, APR
19) is set to 84.
A simple test that you can perform is to change the power of the trans-
mitted signal and observe the I or Q channels with an oscilloscope just
before the ADC’s input. Make sure that the peak-to-peak signal range is
about 1/1.7 of the peak-to-peak ADC range. Also check that the AGC can
keep the signal level fixed even when the transmitted power is changed.
Observe that the AGC voltage at the loop’s output is changing with the
changes in the transmitted power. You may need to switch
the polarity of the PWRP output by toggling the PWRP bit (Group 4,
APR 35).
The following parameters are related to the AGC loop:
PWR_REF[7:0]; Group 4, APR19 – This parameter controls the signal
level at the input of the ADC. It should be set to 84.
PWR_LVL[7:0]; Group 3, APR 8 – This read-only register is propor-
tional to the mean value of the sigma-delta output. If the AGC amplifica-
tion range is 0 dB to -30 dB,
settings and amplification levels.
PWR_LVL
Setting
0
128
255
L64704 Application Notes
Amplification (dB)
0
-15
-30
Table B.2
shows corresponding PWR_LVL