L64704 LSI Logic Corporation, L64704 Datasheet - Page 50

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3-18
APR
0
VBER
7
S3_LS
The register diagram below shows a detailed description of the STS[7:0]
register bits.
VBER
S3_LS
S3_S
S2_LS
L64704 Registers
6
S3_S
5
Viterbi Bit Error Rate Flag
The L64704 sets VBER when the period specified by
VMDC2 (Group 4, APRs 5, 6, and 7) is reached. It also
generates an interrupt if the VBER_IE bit in the SMR is
set. The L64704 clears VBER to zero after a reset or a
Group 2 (STS) read.
Stage 3 Loss of Synchronization Flag
The L64704 sets S3_LS when the Descrambler synchro-
nization module determines that synchronization is lost. It
also generates an interrupt if the S3_LS_IE bit is set in
the SMR. The L64704 clears S3_LS to zero after a reset
or a Group 2 (STS) read.
Stage 3 Synchronization Flag
The L64704 sets S3_S when the Descrambler synchro-
nization module acquires synchronization. It also gener-
ates an interrupt if the S3_S_IE bit is set in the SMR. The
L64704 clears S3_S to zero after a reset or a Group 2
(STS) read.
Stage 2 Loss of Synchronization Flag
The L64704 sets S2_LS when the Deinterleaver/Reed-
Solomon Decoder synchronization module determines
that synchronization is lost. It also generates an interrupt
VBER
0
1
S3_LS
0
1
S3_S
0
1
S2_LS
4
Definition
VMDC2 Period not Reached
VMDC2 Period Reached
Definition
Stage 3 Synchronization Status Unchanged
Loss of Stage 3 Synchronization Detected
Definition
Stage 3 Synchronization Status Unchanged
Stage 3 Synchronization Acquired
S2_S
3
S1_LS
2
S1_S
1
Reserved
0
7
6
5
4