L64704 LSI Logic Corporation, L64704 Datasheet - Page 57

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.5.8
Group 3,
APR 10
RI Readback
S2
S1
This register displays the value on the RI[5:0] input bus. Group 3, RI
values are only correct when the PLL is set such that ICLK = OCLK.
Read/Write: R
Reserved
RI
Group 3 Registers
APR
10
D7
Reserved
Stage 2 Synchronization Flag
The L64704 sets S2 to 1 when the Deinterleaver/Reed-
Solomon Decoder synchronization module is in synchro-
nization. When this bit is 0, the Deinterleaver/Reed-
Solomon Decoder is not synchronized.
Stage 1 Synchronization Flag
The L64704 sets S1 to 1 when the Viterbi Decoder
synchronization module is in synchronization. When this
bit is 0, the Viterbi Decoder is not synchronized.
Reserved Bits
These bits are reserved for LSI Logic internal use only.
When read, they will return an indeterminate value.
RI Readback
This register displays the value on the RI[5:0] input bus.
(Note that OCLK needs to be running for this feature to
operate properly).
S2
0
1
S1
0
1
D6
D5
Definition
Deinterleaver/Reed-Solomon Decoder
Out of Synchronization
Deinterleaver/Reed-Solomon Decoder
In Synchronization
Definition
Viterbi Decoder Out of Synchronization
Viterbi Decoder In Synchronization
D4
D3
RI
D2
Reset Value: 0x00
D1
D0
[7:6]
[5:0]
3-25
1
0