L64704 LSI Logic Corporation, L64704 Datasheet - Page 66

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.10
Group 4,
APR 11
Synchronization
States and
BCLKOUT
Format
3-34
This register is used to select which algorithms will be used in the syn-
chronization modules, and which module’s synchronization status will be
shown on the SYNC output pin. It also selects the frequency of the clock
that will be output on the BCLKOUT pin.
Read/Write: R/W
BF
Set to 0
SSS[1:0]
L64704 Registers
APR
11
D7
BF
Set to 0
BCLKOUT Format
When you set this bit to 1, the BCLKOUT pin outputs a
continuous clock waveform with a 50% duty cycle at 1/8
the OCLK frequency. It is typically used by a downstream
device that runs on a byte-clock rather than on a bit clock.
The DVALIDOUT pin needs to be observed to identify
valid data bytes. When you set this bit to 0, the BCLK-
OUT produces a rising edge for every valid data bit on
the CO0 output pin (Serial Output Channel mode). The
downstream device can use BCLKOUT as a data latching
strobe without the need to inspect DVALIDOUT.
Set to 0
You should set this bit LOW for proper operation.
Synchronization Status Select
You can observe the synchronization status of one of the
three synchronization modules on the SYNC output pin:
Viterbi decoder synchronization, Deinterleaver/Reed-
Solomon decoder synchronization, and Descrambler
synchronization. You program the SSS field to determine
Data Bits
D7
1
0
D6
D5
SSS[1:0]
BCLKOUT
Function:
Continuous Clock
Data Strobe
D4
D3
SSA[1:0]
Operating Mode
Serial Output Channel
Parallel Output Channel
D2
D1
SST[1:0]
D0
[5:4]
7
6