L64704 LSI Logic Corporation, L64704 Datasheet - Page 116
L64704
Manufacturer Part Number
L64704
Description
Satellite Decoder Technical Manual 5/97
Manufacturer
LSI Logic Corporation
Datasheet
1.L64704.pdf
(220 pages)
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5.6.1
Carrier
Acquisition
5-12
The Carrier Synchronizer provides its output to the analog filter through
two
ing on the value of the CAR_VCO1N/P and CAR_VCO2N/P bits (Group
4, APR 33), the Carrier Synchronizer selects one pair and 3-states the
other pair. An analog integrator adds the signals together externally,
where the signals of pair 2 are weighted with a different factor relative to
the signals of pair 1. You choose different values for R
to change the weighting factor (see
tics”). This feature provides a means for adjusting the loop bandwidth
over a larger range than would be possible with pure
During carrier acquisition, the internal frequency sweep generator
searches for the correct frequency. To vary the sweep rate, change the
value in the CAR_SWR register (Group 4, APR 28); to start the sweep
generator, set the CAR_SW bit (Group 4, APR 33) to 1.
5.6.1.1 Frequency Sweep Limits
The CAR_USWL (Group 4, APR 29:30) and CAR_LSWL (Group 4, APR
31:32) registers set the upper and lower limits, respectively, of the fre-
quency sweep.
The frequency sweep uses an external crystal that produces a reference
clock (the same crystal as for clock acquisition). See
lator Cells”
The external prescaler divides the frequency of the carrier VCO by a con-
stant number (32, for example) and then feeds it into the L64704 on the
CAR_DCLK pair of differential input pins. You should design the pres-
caler so that the frequency is faster than the crystal reference frequency
and slower than 80% of the CLK frequency.
The reference period for the VCO frequency measurement ends when a
decrementing reference counter driven by the reference clock reaches
zero. The L64704 loads the counter with the value in the 4-bit CAR_RP
register (Group 4, APR 24). This value defines the reference period in
multiples of 1024 clock cycles.
The prescaled clock drives an incrementing counter within the VCOF
block that is reset at the beginning of the reference period. The VCOF
logic then checks the value of the counter at the end of the reference
period. If the prescaled frequency is below the lower limit set in the
Demodulator Module Functional Description
differential pairs; CAR_VCO1P/N and CAR_VCO2P/N. Depend-
for details.
Section 5.6.2.2, “Loop Characteris-
Appendix C, “Oscil-
CAR1
modulation.
and R
CAR2
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