L64704 LSI Logic Corporation, L64704 Datasheet - Page 69

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.12
Group 4,
APR 13
PLL Reset
3.6.13
Group 4,
APR 14
Clock Loop
Control 1
Writing any value to APR 13 generates an internal reset pulse for the
PLL module. The L64704 ignores any data on the D[7:0] bus during a
write to this register. You should reset the PLL module before operation.
The PLL Reset register (APR 13) cannot be read.
Read/Write: Write Only
The Clock Loop Control 1 register is used to set clock parameters related
to the Demodulator module carrier synchronization logic.
Read/Write: R/W
SYNC/SCLK
Group 4 Registers
APR
APR
13
14
SYNC/
SCLK
D7
D7
Reserved Set to 0
SYNC Pin Output Select
Use this pin to select the signal that you want to appear
on the SYNC pin:
When this bit is set to 0, the SYNC pin carries the signal
selected by the Synchronization Status Select bits
SSS[1:0] (Group 4, APR 11). When this bit is set to 1, the
SYNC pin carries the symbol clock of the demodulator,
SCLK, that is used to clock the external DAC during low
baud rate operation. For more information see Section
5.6.2.3, “Low Baud Rate Operation.”
Data Bits
D2 D1 D0
1
D7
0
1
D6
D6
1
Output
SYNC
SCLK
1
D5
D5
Definition
BPSK/QPSK Demodulator Output
F_OUT_
HiZ
D4
D4
PLL_RESET
When Used
Normal Operation
Low Baud Rate Operations
CLK_LCF
Suppress
D3
D3
CLK_VCO
_SWAP
D2
D2
D1
D1
CLK_DR[1:0]
D0
D0
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