L64704 LSI Logic Corporation, L64704 Datasheet - Page 63

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.5
Group 4,
APR 4
Viterbi Max Data
Bit Count 1
3.6.6
Group 4,
APR 5, 6, 7
Viterbi Max Data
Bit Count 2
SYNC2_MOD Sync 2 Modified
Set to 0
PLL_M
VMDC1 specifies the number of valid symbols, divided by 256, over
which the number of Viterbi decoded symbol errors are counted for
synchronization. For example, a value of VMDC1[7:0] = 0b0000001
specifies 512 data bits. For more information see Section
Bit Error Rate Monitor.”
Read/Write: R/W
VMDC2 specifies the number of valid symbols, divided by 4, over which
the number of symbol errors in the Viterbi output data stream are
counted, after synchronization. The symbol error count is then displayed
as VBERC (Group 3, APR 4:5). The value for VMDC2 occupies 24 bits
and is arranged as three bytes with APR 5, bit 0 being the least signifi-
cant bit and APR 7, bit 7 being the most significant bit. For example, a
value of VMDC2[23:0] = 0x0000F0 specifies 960 data bits. For more
information see Section
Group 4 Registers
APR
4
D7
This bit selects an alternate method of acquiring Sync 2.
It should be set to 1 for normal operation.
Set to 0
This bit must be set to 0 for proper operation.
VCO Frequency Range for PLL Module
PLL_M is one of four parameters (PLL_S, PLL_N, PLL_T,
PLL_M) that you must set to configure the PLL module
for clock synthesis. For more information see Section
“PLL Clock Generation.”
L64704 the frequency range of the VCO.
Data Bits
D1
0
0
1
1
D6
D0
0
1
0
1
7.1.4, “Viterbi Bit Error Rate Monitor.”
D5
Viterbi Maximum Data Bit Count 1
VCO Range
40 - 50 MHz
50 - 60 MHz
60 - 70 MHz
70 - 80 MHz
D4
Set PLL_M[1:0] to tell the
D3
D2
7.1.4, “Viterbi
D1
D0
[1:0]
4.4,
3-31
3
2