L64704 LSI Logic Corporation, L64704 Datasheet - Page 89

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

4.3
Channel Data
Output Interface
Figure 4.6
OCLK Reference
to Channel Data
Output
Figure 4.7
FSTARTOUT
Related to
Symbols
4.4
PLL Clock
Generation
Figure 4.6
OUT, ERROROUT, and FSTARTOUT are referenced to OCLK.
CO[7:0], DVALIDOUT,
Figure 4.7
L64704 asserts DVALIDOUT. The L64704 deasserts DVALIDOUT when
it transfers parity and gap data. When the L64704 detects an uncorrect-
able error, it asserts ERROROUT while it transmits both data and parity
bytes.
FSTARTOUT
The L64704 asserts FSTARTOUT when it transfers the first bit of the first
symbol of every frame. The frame structure does not require a gap, and
the decoding process does not affect the gap bytes.
The data control and clocking schemes presented in
Control and Clocking Schemes,”
ation of the two external clock signals (CLK and OCLK) that are required
by the L64704. You have to choose whether to provide an externally gen-
erated clock to the OCLK input or to use the internal PLL for clock syn-
thesis. The internal PLL is selected by connecting the PLL output pin
(PCLK) to the OCLK input pin as shown in
Channel Data Output Interface
ERROROUT
DVALIDOUT
FSTARTOUT, SYNC
CO[7:0]
ERROROUT,
shows how the channel data output signals CO[7:0], DVALID-
shows that new data is valid on the output whenever the
OCLK
Gap
Output Delay
Data
outline the requirements for the gener-
Figure 4.8
Parity
Section 4.1, “Data
and in
Figure
Gap
4.1.
4-5