L64704 LSI Logic Corporation, L64704 Datasheet - Page 86

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

4.1
Data Control
and Clocking
Schemes
Figure 4.1
L64704 Clocking:
Internal PLL
4-2
VCO
A
D
C
CLK
RQ
RI
The L64704 uses two input clock signals, CLK and OCLK, to accommo-
date a number of possible configurations in a channel decoding system.
CLK is generated by the external Clock VCO and can be two, three, or
four times the symbol rate. There is also an internally generated symbol
clock, SCLK.
OCLK is the Forward Error Correction clock. Its relation to CLK is
determined by the Viterbi puncture rate and the number of samples per
symbol at the ADC. An on-chip PLL generates the desired OCLK
frequency and outputs it to the PCLK output (see
connect the PCLK output pin to the OCLK input pin.
You can also generate the desired OCLK signal using an external PLL
(see
symbol rate clock, SCLK. The external PLL frequency is a function of the
Viterbi puncture rate.
Channel Interfaces and Data Control
L64704
Figure
Demodulator
4.2). In that case the PCLK pin should be set to output the
DEMQ
DEMI
SCLK
PCLK Selected
PLL
PCLK
PCLK
Figure
O
F
F
I
FEC
4.1). You should
OCLK