L64704 LSI Logic Corporation, L64704 Datasheet - Page 68

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.11
Group 4,
APR 12
Output Control
3-36
This register is used to configure the Channel output data path.
Read/Write: R/W
BPS[2:0]
Set to 0
OF
OS[2:0]
L64704 Registers
APR
12
D7
BPS[2:0]
Symbol Size for Viterbi Bypass Mode
You should set these bits to 0 for proper operation.
Set to 0
You should set this bit to 0 for proper operation.
Descrambler Output Format
Writing to this bit sets the descrambler output mode:
In Serial Channel Output mode, one bit of decoded data
is presented on CO0 every OCLK cycle. In Parallel Chan-
nel Output mode, one byte of decoded data is presented
on CO[7:0] every eight OCLK cycles.
Output Selector
The output of several major functional blocks can be
observed on the channel output (CO[7:0] in Parallel
Channel Output mode, CO0 in Serial Channel Output
mode). For a detailed description of the signals observed
for the cases below, see Section
Configurations.”
D3 Data Bit CO[7:0] Channel Output Mode
0
1
Data Bits
D2 D1 D0
0
0
0
0
1
1
1
D6
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D5
Definition
Descrambler Module Output
Descrambler Module Synchronization (Sync 3)
Output
RS Decoder Output
Deinterleaver Module Output
Deinterleaver/RS Synchronization (Sync 2) Output
Viterbi Decoder Module Output
Viterbi Synchronization/Decoder Synchronization
(Sync 1) Output
Serial Channel Output Mode
Parallel Channel Output Mode
Set to 0
D4
OF
D3
4.5, “Data Path Output
D2
OS[2:0]
D1
D0
[7:5]
[2:0]
4
3