L64704 LSI Logic Corporation, L64704 Datasheet - Page 74

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

3.6.19
Group 4,
APR 21
Scale Factor for
DEMI and
DEMQ Outputs
3.6.20
Group 4,
APR 22
SNR Estimator
Threshold
3.6.21
Group 4,
APR 23
Carrier Loop DC
Offset
Compensation
Value
3-42
PWR_BW[1:0] Power Estimation Bandwidth
Program these bits to set the scale factor for the DEMI and DEMQ
outputs from the Demodulator to the FEC Decoder. For a relationship
between SCALE and PWR_REF, see Section
Read/Write: R/W
Use this register to set the value that the phase detector’s Signal to
Noise Ratio (SNR) comparator uses as a threshold when deciding which
gain value to use. For details, see
Phase Tracking.”
Read/Write: R/W
Use this register to establish a DC offset voltage that is added to or sub-
tracted from the carrier loop voltage. The value stored in this register is
a signed integer that ranges from -128 to +127. For details, see Section
5.9.1, “Carrier Loop DC Offset Compensation.”
L64704 Registers
APR
APR
21
22
D7
D7
Program these bits to set the power estimation band-
width. For more information see Section
Control Loop.”
D1
0
0
1
1
D6
D6
D0
0
1
0
1
D5
D5
Symbol Rate (MHz)
20 - 45
10 - 20
5 - 10
2 - 5
SNR_THS[7:0]
D4
D4
SCALE[7:0]
Figure 5.7
D3
D3
in Section
5.8, “Output Control.”
D2
D2
5.7.2, “Power
5.6.2, “Carrier
D1
D1
D0
D0
[1:0]