st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 105

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
10.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
Alternate counter register (ACR)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR),
alternate counter register) on page
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table
clock cycles depending on the CC[1:0] bits. The timer frequency can be f
f
CPU
/8 or an external frequency.
Counter high register (CHR) is the most significant byte (MSB).
Counter low register (CLR) is the least significant byte (LSB).
Alternate counter high register (ACHR) is the MSB.
Alternate counter low register (ACLR) is the LSB.
51. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU
(see16-bit read sequence (from either the counter register or the
107).
On-chip peripherals
CPU
/2, f
CPU
/4,
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