st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 153

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Table 62.
SCI control register 1 (SCICR1)
1. This bit has a different function in LIN mode; please refer to
Bit Name
SCICR1
3
2
1
0
R/W
R8
7
OR
NF
PE
FE
Overrun error
Character noise flag
Framing error
Parity error
SCISR register description (continued)
The OR bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register whereas RDRF is still set. An
interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error detected
Note: When this bit is set, RDR register contents are not lost but the shift register is
overwritten.
This bit is set by hardware when noise is detected on a received character. It is
cleared by a software sequence (an access to the SCISR register followed by a read
to the SCIDR register).
0: No noise
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the RDRF
bit which itself generates an interrupt.
This bit is set by hardware when a desynchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No framing error
1: Framing error or break character detected
Note: This bit does not generate an interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred
causes both a frame error and an overrun error, it is transferred and only the OR bit is
set.
This bit is set by hardware when a byte parity error occurs (if the PCE bit is set) in
receiver mode. It is cleared by a software sequence (a read to the status register
followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No parity error
1: Parity error detected
R/W
T8
6
SCID
R/W
5
R/W
M
4
Function
WAKE
R/W
3
Section 10.5.10: LIN mode registers
PCE
R/W
2
(1)
Reset value: x000 0000 (x0h)
On-chip peripherals
R/W
PS
1
R/W
PIE
153/371
0