st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 157

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Table 65.
SCI extended receive prescaler division register (SCIERPR)
Table 66.
7:6 SCP[1:0]
5:3 SCT[2:0]
2:0 SCR[2:0]
SCIERPR
7:0 ERPR[7:0]
Bit
Bit
7
Name
Name
SCIBRR register description
SCIERPR register description
First SCI prescaler
SCI transmitter rate divisor
SCI receiver rate divider
8-bit extended receive prescaler register
6
These 2 prescaling bits allow several standard clock division ranges:
00: PR prescaling factor = 1
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
generator mode:
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied
to the bus clock to yield the receive rate clock in conventional baud rate generator
mode:
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
The extended baud rate generator is activated when a value other than 00h is
stored in this register. The clock frequency from the 16 divider (see
divided by the binary factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
5
4
ERPR[7:0]
R/W
Function
Function
3
2
Reset value: 0000 0000 (00h)
On-chip peripherals
1
Figure
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0