st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 91

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
10.1.8
10.1.9
10.1.10
10.1.11
Using Halt mode with the watchdog (WDGHALT option)
If Halt mode is used when the watchdog is enabled, refresh the WDG counter before
executing the HALT instruction to avoid an unexpected WDG reset immediately after waking
up the microcontroller.
Watchdog interrupts
None.
Watchdog control register (WDGCR)
Table 35.
Watchdog window register (WDGWR)
Table 36.
WDGCR
WDGWR
6:0 W[6:0]
Bit Name
Bit
6:0
Reserved
7
7
WDGA
R/W
7
7
-
WDGA
Name
T[6:0]
-
Reserved, must be kept cleared
7-bit window value
WDGCR register description
WDGWR register description
These bits contain the window value to be compared to the downcounter.
Activation bit
7-bit counter (MSB to LSB)
6
6
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option
byte.
These bits contain the value of the watchdog counter. It is decremented every
16384 f
3Fh (T6 becomes cleared).
OSC2
5
5
cycles (approx). A reset is produced when it rolls over from 40h to
4
4
Function
W[6:0]
Function
T[6:0]
R/W
R/W
3
3
2
2
Reset value: 0111 1111 (7Fh)
Reset value: 0111 1111 (7Fh)
On-chip peripherals
1
1
0
0
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