st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 115

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure 50. One pulse mode sequence
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Equation 3
Where:
t =
f
PRESC
If the timer clock is an external clock the formula is:
Equation 4
Where:
t =
f
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see
CPU
EXT
Reading the SR register while the ICFi bit is set.
Accessing (reading or writing) the ICiLR register.
=
=
=
OCiR =
pulse period (in seconds)
CPU clock frequency (in hertz)
timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see
pulse period (in seconds)
external timer clock frequency (in hertz)
t
*
f
EXT
-5
When event
occurs on
OCiR value =
= OC1R
ICAP1
counter
When
Figure
One pulse mode cycle
PRESC
t
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
*
ICR1 = counter
ICF1 bit is set
f
CPU
to FFFCh
51).
- 5
On-chip peripherals
Table
115/371
51)