st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 266

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
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Table 126. MCRA register description (continued)
1. The reset state is either high impedance, high or low state depending on the corresponding option bit.
2. When the MOE bit in the MCRA register is reset (MCOx outputs in reset state), and the SR bit in the MCRA
Bit Name
6
5
4
3
2
1
0
register is reset (sensorless mode) and the SPLG bit in the MCRC register is reset (sampling at PWM
frequency) then, depending on the state of the ZSV bit in the MSCR register, Z event sampling can run or
be stopped (and D event is sampled).
V0C1
SWA
CKE
DCB
DAC
SR
PZ
Clock enable bit
Sensor ON/OFF
Direct access to phase state register
Voltage/current mode
Switched/autoswitched mode
Protection from parasitic zero-crossing event detection
Data capture bit
0: Motor control peripheral clocks disabled
1: Motor control peripheral clocks enabled
Note: ‘Clocks disabled’ means that all peripheral internal clocks (delay manager,
internal sampling clock, PWM generator) are disabled. Therefore, the peripheral can
no longer detect events and the preload registers do not operate. When clocks are
disabled, write accesses are allowed, so for example, MTIM counter register can be
reset by software. See
0: Sensorless mode
1: Position sensor mode
See
0: No direct access (reset value). In this mode the preload value of the MPHST and
1: Direct access enabled. In this mode, write a value in the MPHST register to access
See
Note: In direct access mode (DAC bit is set in MCRA register), a C event is generated
as soon as there is a write access to the OO[5:0] bits in MPHST register. In this case,
the PWM low/high selection is done by the OS0 bit in the MCRB register.
0: Voltage mode
1: Current mode
0: Switched mode
1: Autoswitched mode
Notes:
1. After reset, in autoswitched mode (SWA = 1), the motor control peripheral is waiting
2. After reset, a C event is immediately generated when CKE and SWA are
0: Protection disabled
1: Protection enabled
Note: If the PZ bit is set, the Z event filter (ZEF[3:0] in the MZFR register is ignored.
0: Use MZPRV (Z
1: Use MZREG (Z
See
for a C commutation event.
simultaneously set due to a nil value of MCOMP.
MCRB registers is taken into account at the C event
the outputs directly
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Table
Table
Table
128,
129.
130.
Table 133
N
N
-1) for multiplication
) for multiplication
Table
and
127.
Table
134.
Function