st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 76

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Power saving modes
8.4.2
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Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the main clock controller status register
(MCCSR) is cleared (see
The MCU can exit Halt mode on reception of either a specific interrupt
Interrupt mapping on page
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see
more details).
Figure 26. HALT timing overview
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
[MCCSR.OIE = 0]
Run
instruction
HALT
Section 6.6 on page 54
70) or a reset. When exiting Halt mode by means of a reset or an
HALT
256 or 4096 CPU
cycle delay
interrupt
Reset
or
for more details on the MCCSR register).
vector
Section 14.1 on page 356
Fetch
Run
(seeTable 22:
Figure
27).
for