st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 52

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Supply, reset and clock management
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Table 9.
Application notes
The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Bit
5
4
3
2
1
0
WDGRF
LVDRF
CSSIE
Name
CSSD
AVDF
-
SICSR (page 0) register description (continued)
Voltage detector flag
LVD reset flag
Reserved, must be kept cleared
Clock security system interrupt enable
Clock security system detection
Watchdog reset flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit changes value.
0: V
1: V
This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by option byte, the LVDRF bit
value is undefined.
This bit enables the interrupt when a disturbance is detected by the clock security
system (CSSD bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the PLL is disabled (PLLEN = 0), the CSSIE bit has no effect.
This bit indicates a disturbance on the main clock signal (f
least for a few cycles). It is set by hardware and cleared by reading the SICSR
register when the original oscillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the PLL is disabled (PLLEN = 0), the CSSD bit value must be kept cleared.
This bit indicates that the last reset was generated by the watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given below:
00: Reset sources = external RESET pin
01: Reset sources = WDG
1X: Reset sources = LVD
DD
DD
under V
over V
IT+ (AVD)
IT-(AVD)
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto,
threshold
threshold
Function
OSC
): The clock stops (at