st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 265

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Note:
2
3
1
Table 125. MISR register description (continued)
Loading value FFh in the MISR register resets the PWM generator counter and transfers the
compare preload registers in the active registers by generating a U event (PUI bit set to 1).
Refer to
When several MTC interrupts are enabled at the same time the BRES instruction must not
be used to avoid unwanted clearing of status flags: if a second interrupt occurs while BRES
is executed (which performs a read-modify-write sequence) to clear the flag of a first
interrupt, the flag of the second interrupt may also be cleared and the corresponding
interrupt routine is not serviced. It is thus recommended to use a load instruction to clear the
flag, with a value equal to the logical complement of the bit. For instance, to clear the PUI
flag:
ld MISR, # 0x7F.
In autoswitched mode (SWA = 1 in the MRCA register): As all bits in the MISR register are
status flags, they are set by internal hardware signals and must be cleared by software. Any
attempt to write them to 1 has no effect (they are read as 0) without interrupt generation.
In switched mode (SWA = 0 in the MRCA register): To avoid losing any interrupts when
modifying the RMI and RPI bits the following instruction sequence is recommended:
ld MISR, # 0x9F; reset both RMI and RPI bits.
ld MISR, # 0xBF; set RMI bit.
ld MISR, # 0xDF; set RPI bit.
Control register A (MCRA)
Table 126. MCRA register description
Bit Name
MCRA
Bit Name
1
0
7
MOE
R/W
7
MOE
DI
CI
Timer resynchronization on page
End of demagnetization interrupt flag
Commutation/capture interrupt flag
Output enable bit
0: No end of demagnetization interrupt pending
1: End of demagnetization interrupt pending
0: No commutation/capture interrupt pending
1: Commutation/capture interrupt pending
0: Outputs disabled; MC0[5:0] outputs are put in reset state
1: Outputs enabled; MC0[5:0] outputs enabled
CKE
R/W
6
R/W
SR
5
DAC
R/W
4
258.
Function
Function
V0C1
R/W
3
SWA
R/W
2
Reset value: 0000 0000 (00h)
(1)(2)
On-chip peripherals
R/W
PZ
1
DCB
R/W
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0