st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 136

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
10.4.7
Note:
10.4.8
136/371
Interrupts
Table 55.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
SPI registers
SPI control register (SPICR)
Table 56.
SPI end of transfer event
Master mode fault event
Overrun error
SPICR
Bit
7
6
5
SPIE
R/W
7
Interrupt event
Name
SPR2
SPIE
SPE
SPI interrupt control/wake-up capability
SPICR register description
Serial peripheral interrupt enable
Serial peripheral output enable
Divider enable
SPE
R/W
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an end of transfer event, master mode
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
cleared by reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset.
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit is used with the SPR[1:0] bits to set the baud rate:
100: Serial clock = f
000: Serial clock = f
001: Serial clock = f
110: Serial clock = f
010: Serial clock = f
011: Serial clock = f
This bit has no effect in slave mode.
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
fault or overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR
register).
SPR2
Event flag
R/W
5
MODF
SPIF
OVR
CPU
CPU
CPU
CPU
CPU
CPU
MSTR
/4
/8
/16
/32
/64
/128
R/W
Enable control bit
4
Master mode fault (MODF) on page
SPIE
Function
CPOL
R/W
3
Exit from WAIT
CPHA
R/W
2
Reset value: 0000 xxxx (0xh)
Yes
133). The SPE bit is
1
Exit from HALT
SPR[1:0]
R/W
Yes
No
0