st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 344

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st7pmc2s6

Manufacturer Part Number
st7pmc2s6
Description
8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
Manufacturer
STMicroelectronics
Datasheet
Electrical characteristics
12.12.3
Table 218. Input stage (current feedback comparator and sampling)
1. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the
2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.
3. This delay represents the number of clock cycles needed to generate an event as soon as the comparator output changes.
344/371
Symbol
t
comparator and must be avoided:
Negative injection current on the I/Os close to the comparator inputs
Switching on I/Os close to the comparator inputs
Negative injection current on not used comparator input (MCCFI0 or MCCFI1)
Switching with a high dV/dt on not used comparator input (MCCFI0 or MCCFI1)
These phenomena are even more critical when a big external serial resistor is added on the inputs.
Example: When CFF = 0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle
after comparator commutation, that is, there is a variation of (1 / f
sampling
t
t
V
I
propag
startup
offset
V
offset
IN
Input stage (current feedback comparator and sampling)
Comparator input voltage
range
Comparator offset error
Input offset current
Comparator propagation
delay
Start-up filter duration
Digital sampling delay
(1)
Parameter
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
(2)
(3)
Time waited before sampling
when comparator is turned
ON, that is, CKE
DAC
f
Time needed to turn OFF the
MCOs when comparator
output rises (CFF = 0)
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF = 0)
Time needed to turn OFF the
MCOs when comparator
output rises (CFF = x)
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF = x)
PERIPH
=
1 (with
= 4 MHz)
Conditions
=
mtc
1 or
) or (4/f
PERIPH
V
SSA
Min
) depending on the case.
- 0.1
(1 + x) * (4/f
(1 + x) * (4/f
4/f
2/f
MTC
MTC
(see
(see
Typ
35
5
(see
(see
3
Figure
Figure
PERIPH
PERIPH
Figure
Figure
V
157)
157)
) + (3/f
) + (1/f
DD
40
Max
100
156)
156)
1
+ 0.1
(1)
mtc
mtc
)
)
Unit
mV
µA
ns
µs
V

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