st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 198

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by
comparing the MTIM timer with the MDREG register. This kind of demagnetization is called simulated
demagnetization D
If the HDM and SDM bits are both set, the first event that occurs, triggers a demagnetization event. For
this to work correctly, a D
Z event.
Simulated demagnetization can also be always used if the HDM bit is reset and the SDM bit is set. This
mode works as a programmable masking time between the C
the masking time must be always greater than the real demagnetization time in order to avoid a spurious
Z event.
When an event occurs, (either D
generated if the DIM bit of register MIMR is set.
Caution:
Caution:
Figure 82. D event generation mechanism
1. Preload bit, new value taken into account at the next C event (in normal mode) or when a value is written in the MPHST
2.
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SPLG bit
register
MCRC
HDM bit
SDM bit
Sample
register when in direct access mode. For more details refer to the description of the DAC bit in
on page
Register updated on R event
C
D
S,H
D
D
S
H
265. The use of a preload register allows all the registers to be updated at the same time
2
1
1: Due to the alternate automatic capture and compare of the MTIM timer with MDREG
register by D
2: Due to the event generation protection in the MZREG, MCOMP and MDREG registers for
Soft Event generation (see
the value written in the MDREG register in soft demagnetization mode (SDM = 1) is checked
by hardware after the C event. If this value is less than or equal to the MTIM counter value at
this moment, the Software demagnetization event is generated immediately and the MTIM
current value overwrites the value in the MDREG register to be able to re-use the right
demagnetization time for another simulated event generation.
CPB
F(x)
S
or
n
To Z event detection
MCRB register
.
bit
(1)
S
H
HDM
event must not precede a D
and D
n
D = D
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
bit
(1)
H
S
H
or D
and HDM bit + D
events, the MDREG register should be manipulated with special care.
MCRA register
S
SR bit
) the DI bit in the MISR register is set and an interrupt request is
Built-in checks and controls for simulated events on page
S
and SDM bit
H
event because the latter could be detected as a
D
H
H
and Z events. To drive the motor securely,
MDFR register
MCRB register
DWF[3:0]
DEF[3:0]
SDM
(1)
bit
D
H
MTIM [8-bit up counter]
MDREG [D
To interrupt generator
Control register A (MCRA)
Compare
8
n
D
]
(2)
D
S
MDFR register
(2)
DWF[3:0]
221),