st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 169

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
10.5.10
Error due to baud rate quantization
The baud rate can be adjusted in steps of 1/(16 * LDIV). The worst case occurs when the
‘real’ baud rate is in the middle of a step.
This leads to a quantization error (D
Impact of clock deviation on maximum baud rate
The choice of the nominal baud rate (LDIV
(D
Consequently, at a given CPU frequency, the maximum possible nominal baud rate
(LPR
equation:
D
Example:
A nominal baud rate of 20Kbits/s at T
LDIV
D
D
LIN slave systems
For LIN slave systems (the LINE and LSLV bits are set), receivers wake up by LIN synch
break or LIN identifier detection (depending on the LHDM bit).
Hot plugging feature for LIN slave nodes
In LIN slave mute mode (the LINE, LSLV and RWU bits are set) it is possible to hot plug to a
network during an ongoing communication flow. In this case the SCI monitors the bus on the
RDI line until 11 consecutive dominant bits have been detected and discards all the other
bits received.
LIN mode registers
SCI status register (SCISR)
SCISR
TRA
MEAS
QUANT
QUANT
TDRE
RO
MIN
MIN
7
+ 2/(128*LDIV
= 2/(128*LDIV
) should be chosen with respect to the maximum tolerated deviation given by the
= 1/(2*16*LDIV
) and the measurement error (D
= 25 - 0.15*25 = 21.25
RO
TC
6
MIN
MIN
) + 1/(2*16*LDIV
MIN
) * 100 = 0.00073%
RDRF
) * 100 = 0.0015%
RO
5
QUANT
CPU
IDLE
RO
4
MIN
MEAS
= 125ns (8 MHz) leads to LDIV
) equal to 1/(2*16*LDIV
NOM
) + D
). The worst case occurs for LDIV
) influences both the quantization error
REC
LHE
RO
3
+ D
TCL
< 3.75%
RO
NF
2
Reset value: 1100 0000 (C0h)
MIN
).
On-chip peripherals
NOM
RO
FE
1
= 25d.
MIN
.
169/371
RO
PE
0