st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 366

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Known limitations
15.5
15.6
15.7
15.8
366/371
Missing detection of BLDC ‘Z event’
For a BLDC drive, the deadtime generator is enabled through the MDTG register (PCN = 0
and DTE = 1). If the duty cycle of the PWM signal generated to drive the motor is lower than
the programmed deadtime, the Z event sampling is missing.
Workaround
The complementary PWM must be disabled by resetting the DTE bit in the MDTG register
(see
As the current in the motor is very low in this case, the MOSFET body diode can be used.
Reset value of unavailable pins
On rev. A silicon versions, some ports (ports A, C and E) have fewer than eight pins. The
bits associated to the unavailable pins must always be kept at reset state.
Maximum values of AVD thresholds
On rev. A silicon versions, the maximum values of AVD thresholds are not tested in
production.
External interrupt missed
To avoid any risk if generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period is not detected and an interrupt is not generated.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra push instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1
cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to '1' before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked and if it is '1' this means that the last interrupt has been
missed. In this case, the interrupt routine is invoked with the call instruction.
There is another possible case, that is, if writing to PxOR or PxDDR is done with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to '1'
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
Deadtime generator register (MDTG) on page
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
280).