st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 156

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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Table 64.
SCI data register (SCIDR)
The data register contains the received or transmitted data character, depending on whether
it is read from or written to.
This register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
SCI baud rate register (SCIBRR)
When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
Bit Name
SCIDR
SCIBRR
1
0
7
7
RWU
SBK
SCP[1:0]
R/W
Receiver wake-up
Send break
SCICR2 register description (continued)
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
Notes:
- Before selecting mute mode (by setting the RWU bit) the SCI must first receive a
- In Address Mark Detection Wake-up configuration (WAKE bit = 1) the RWU bit
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word at
the end of the current word.
data byte, otherwise it cannot function in mute mode with wakeup by Idle line
detection.
cannot be modified by software while the RDRF bit is set.
6
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure
Figure
61).
61).
5
5
SCT[2:0]
R/W
4
4
DR[7:0]
R/W
Function
3
3
2
2
Reset value: 0000 0000 (00h)
Reset value: undefined
SCR[2:0]
R/W
1
1
0
0