st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 127
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st7pmc2s6
Manufacturer Part Number
st7pmc2s6
Description
8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
Manufacturer
STMicroelectronics
Datasheet
1.ST7PMC2S6.pdf
(371 pages)
- Current page: 127 of 371
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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
10.4
10.4.1
10.4.2
Note:
10.4.3
Serial peripheral interface (SPI)
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.
Main features
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
General description
Figure 54 on page 128
three registers:
The SPI is connected to external devices through four pins:
Full duplex synchronous transfers (on three lines)
Simplex synchronous transfers (on two lines)
Master or slave operation
6 master mode frequencies (f
f
SS management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, master mode fault and overrun flags
SPI control register (SPICR)
SPI control/status register (SPICSR)
SPI data register (SPIDR)
MISO: master in/slave out data
MOSI: master out/slave in data
SCK: serial clock out by SPI masters and input by SPI slaves
SS: slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master device.
CPU
/2 max; slave mode frequency (see note below)
shows the serial peripheral interface (SPI) block diagram. There are
CPU
/4 max.)
On-chip peripherals
127/371
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