st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 129

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure 55. Single master/single slave application
Slave select management
As an alternative to using the SS pin to control the slave select signal, the application can choose to
manage the slave select signal by software. This is configured by the SSM bit in the SPICSR register
(see
In software management, the external SS pin is free for other application uses and the internal SS signal
level is driven by writing to the SSI bit in the SPICSR register.
In master mode SS internal must be held high continuously.
In slave mode, there are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on second clock edge)
If CPHA = 0 (data latched on first clock edge)
Figure 56. Generic SS timing diagram
SS internal must be held low during the entire transmission. This implies that in single slave
applications the SS pin either can be tied to V
function by software (SSM = 1 and SSI = 0 in the in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between each byte to allow
the slave to write to the shift register. If SS is not pulled high, a write collision error occurs when the
slave writes to the shift register (see
Figure
MSBit
SPI clock
generator
57).
8-bit shift register
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Slave SS
Slave SS
Master SS
Master
LSBit
Byte 1
Write collision error (WCOL) on page
SCK
MISO
SS
MOSI
+5V
SS
, or made free for standard I/O by managing the SS
Byte 2
MISO
MOSI
SCK
SS
Byte 3
MSBit
by software
Not used if SS is managed
8-bit shift register
133).
Slave
On-chip peripherals
Figure
LSBit
56):
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