st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 257

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure 122. Comparison between 12-bit and 8-bit PWM mode
Repetition down-counter
Both in center-aligned and edge-aligned modes, the four compare registers (one compare 0
and three for the U, V and W phases) are updated when the PWM counter underflow or
overflow and the 8-bit repetition down-counter has reached zero.
This means that data are transferred from the preload compare registers to the compare
registers every N cycles of the PWM Counter, where N is the value of the 8-bit repetition
register in edge -aligned mode. When using center-aligned mode, the repetition down-
counter is decremented every time the PWM counter overflows or underflows. Although this
limits the maximum number of repetition to 128 PWM cycles, this makes it possible to
update the duty cycle twice per PWM period. As a result, the effective PWM resolution in
that case is equal to the resolution we can get using edge-aligned mode, that is, one T
period. When refreshing compare registers only once per PWM period in center-aligned
mode, maximum resolution is 2xT
The repetition down counter is an auto-reload type; the repetition rate is maintained as
defined by the MREP register value (refer to
PWM interrupt generation
A PWM interrupt is generated synchronously with the ‘U’ update event, which allows to
refresh compare values by software before the next update event. As a result, the refresh
rate for phases duty cycles is directly linked to MREP register setting.
A signal reflecting the update events may be output on a standard I/O port for debugging
purposes. Refer to
12-bit PWM mode
8-bit PWM mode
(PMS bit = 0)
(PMS bit = 1)
Debug option on page 219
Ov
fX
MCMP0H
MCMPxH
MCMP0H
MCMPxH
Ext
b7
b7
b7
MPCR
b7
b7
Ov
fU
Ov
fV fW
Ov
mtc
, due to the symmetry of the pattern.
b0
b0
b0
b0
b0
Figure
MCMP0L
MCMPxL
MCMP0L
MCMPxL
b7
b7
b7
b7
for more details.
123).
Ext
Equivalent bit location
Bit extending comparison range
Bit not available
b0
b0
b0
b0
PWM frequency set-up
Phase x duty cycle set-up
PWM frequency set-up
Phase x duty cycle set-up
On-chip peripherals
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