pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 121

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
PS/2 Interface Operation
The PS/2 interface has two basic operating methods: with the shift mechanism disabled and with the shift mechanism en-
abled. The following sections describe how to use the PS/2 interface with each of these operating methods.
4.6.3
The shift mechanism is disabled when EN bit in PSCON register is cleared (0). In this state, the PS/2 clock and data signals
are controlled by the firmware, which performs the PS/2 protocol by manipulating the PS/2 clock and data signals.
Clock Signal Control
CLK4-1 bits in PSOSIG register control the value of the respective clock signals (PSCLK4-1). When one of these bits is
cleared (0), the relevant pin is held low. When set (1), the open-drain output is open and the respective clock signal is either
floating or held high by the pull-up. In this case, an external device can force the respective clock signal low.
When reading PSISIG register, bits RCLK4-1 indicate the current state of the corresponding clock signal.
Data Signal Control
WDAT4-1 bits in PSOSIG register control the value of the respective data signals (PSDAT4-1). When one of these bits is
cleared (0), the relevant data signal is held low. When set (1), the open-drain output is open and the respective data signal
is held high by the pull-up. In this case, an external device can force the respective data signal low.
When reading PSISIG register, bits RDAT4-1 indicate the current state of the corresponding data signal.
Interrupt Generation
When DSMIE bit in PSIEN register is set (1), the clock input signals are connected to the Interrupt Control Unit (ICU) for an
interrupt driven PS/2 protocol. The four interrupts that are generated are PSINT4-1 for channels 4-1, respectively.
The ICU should be programed to detect a falling edge on each of the clock signals. Disabling a channel by writing 0 to the
clock control signals (CLK4-1) may cause a falling edge on a clock signal. When such an interrupt is not desired, clear the
clock control bit (0); then clear the respective pending bit in the ICU (or in the MIWU, for PSINT4). This should be done while
interrupts are disabled. For more details about the ICU, see Section 4.3 on page 96.
4.6.4
The shift mechanism is designed to off load the bit level handling of the data transfer from the firmware to a hardware
scheme; this improves system tolerance to interrupt latency. The mechanism includes a shift register and a state machine
that controls the PS/2 protocol.
Figure 40 shows the shift mechanism PS/2 data transfer sequence. There are three basic modes: Disabled, Receive and
Transmit. Different states in each mode define the progress of the data transfer. The rest of this section details the use of
the shift mechanism for implementing a PS/2 data transfer.
Operating With the Shift Mechanism Disabled
Operating With the Shift Mechanism Enabled
(Continued)
121
www.national.com